A high-level modeling system (HLMS) facilitates circuit design through high-level abstraction of low-level hardware, e.g., circuit components and intellectual property (IP) cores. Generally, an IP core refers to a pre-designed, programmatic description of hardware that performs a particular function. The IP core can be specified as a hardware description language file or files, as a bitstream that programs a programmable integrated circuit device (IC), whether fully or partially programmable, as a netlist, or the like. Alternatively, an IP core can include source code or schematics that describe the logic and connectivity of a portion of a circuit design. Typical IP cores can provide, but are not limited to, digital signal processing (DSP) functions, memories, storage elements, math functions, etc. Some IP cores include an optimally floorplanned layout targeted to a specific family of ICs. Cores can also be parameterizable in that the user may enter parameters to activate or change certain functionality of the IP core.
One benefit of a HLMS is the graphical design environment provided for circuit designers, e.g., users. Working within a HLMS, a user may simply drag and drop various graphical blocks from a library of such blocks into the design environment of the HLMS. Each graphical block represents a high-level modeling block that is representative of a circuit function, e.g., an adder or a multiplier. The user may graphically create wires linking the graphical blocks as well as manually position the graphical blocks within the HLMS design environment using a pointer device.
Once the circuit design is visually created within the HLMS design environment, the user may simulate various aspects of the circuit design, e.g., timing, directly within the HLMS. Additionally, the HLMS may generate any of a variety of different programmatic descriptions for use in implementing the circuit design within an IC. For example, the HLMS may translate the high-level circuit description used natively within the HLMS, e.g., the collection of modeling blocks, into a hardware description language (HDL) formatted circuit description, a netlist, a bitstream that can program a programmable IC, whether fully or partially programmable, or another low-level hardware implementation.
The graphical user interface (GUI) provided by many HLMSs offers several advantages. One advantage is that the drag-and-drop manner in which modeling blocks are added to a system and positioned is straightforward and intuitive for hardware engineers. Graphical representations of circuit designs also facilitate debugging since a user may examine data flowing across graphical blocks. For example, input ports and/or output ports of the system may be graphically linked to data analysis blocks to facilitate cycle-accurate observation of selected signals within the circuit design being modeled.
Unfortunately, GUIs are not scalable when designing very large, complex systems. Such systems may contain thousands of blocks, making graphical design cumbersome and, in some cases, unmanageable as the user is left having to manually and graphically drag each desired modeling block into the HLMS design environment. Additionally, parameterized designs do not lend themselves to graphical design. Within a parameterized design, the number of modeling blocks and the connections between the modeling blocks can change according to the different parameters that may be used. The graphical design environment provided by a HLMS may actually limit the user's ability to fully exploit parameterizable IP cores by making it cumbersome to explore different design and parameterization possibilities.